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Amlan Nag

Amlan Nag

Amlan Nag

Bio

Amlan Nag received the B.Eng. degree in Electronics and Communication engineering from the National Institute of Technology, Silchar, India between 2007-2011). He subsequently served as a visiting researcher at Indian Institute of Technology Guwahati (2009-2010), VLSI Circuit Design Lab where he was involved in designing low power current mode circuits for biomedical applications, like WTA(Winner Take All Circuit), Current Conveyor etc. Amlan then joined Sankalp Semiconductor Pvt., Ltd.(2011-2013), Bengaluru, India, where he was involved in designing high speed clocking architectures like PLL(Phase Lock Loop), DLL(Delay Lock Loop) etc.
Amlan received his Masters Degree in Integrated Circuit & Systems from University of Alberta, (2014-2016) where his research activities included the design and development of high-speed multimode SERDES (PAM2/PAM4/Duobinary) circuits and various frequency synthesizers like ADPLL(All Digital PLL), Subsampling PLL, ILO(Injection Locked Oscillator), etc. During this time Amlan also worked with M/A-COM Technology Solutions, Toronto, Canada, for a four months period in 2015, where I was involved in designing BiCMOS drivers for 100 GBPS transceivers.
Since then Amlan National Institute of Technology, Silchar, India joined as Assistant Professor in Electronics and Communication engineering (2017-2018). Apart from teaching, he was actively involved in the moderation and evaluation of undergrad/grad final year thesis.

Qualification

Masters Degree in Integrated Circuit & Systems

Project

RP7: Readout electronics for sensor interface (ESR7, UEDIN)
The multisensory system requires a dedicated readout electronics, which is designed for wide range of operation (e.g. in terms of temperature, pressure etc.). ESR7 will design low-power sensor interface with blocks for sensing, digitization and wireless communication. The chips will be fabricated in a standard CMOS process and for better integration they will be thinned down to ultra-thin regime (<40┬Ám). This will add new dimension to conventional CMOS technology and thinned chips can also conform to curved surfaces. Various thinning techniques like back-grinding, dry/wet etching etc. will be investigated depending on the chip specification and requirements. Once the system is developed, the performance will be evaluated, and the data will be wirelessly transmitted to the data collection unit. A modular approach for sensors and signal processing electronics will be implemented. Initially off-the-shelf components will be used. The necessary bias and reference circuits to the drive the sensors will be studied and the issues with temperature will be investigated. Custom sensors will be tested using high- precision amplifiers such as INA338. In parallel, the analogue frontend (AFE) signal processing blocks will be developed, such that they can also withstand the harsh environmental conditions. The read-out-electronics will be characterized both with wired and wireless condition to detect the limitations of intermittent and variable power supply.

Project Supervisor
Host Institute

University of Edinburgh, United Kingdom